SAMSUNG SEMICONDUCTOR INC. OVERVIEW:

Samsung Semiconductor Inc. (SSI) is advancing the worlds technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. By seeking the diverse perspectives of our counterparts around the world, we collaborate to make a global impact. We are looking for team members who share our commitment to learning and growth as well as our desire to build personal connections along the way.

SSI is headquartered in the heart of Silicon Valley and is a wholly-owned U.S. subsidiary of Samsung Electronics Co., Ltd.- the #1 employer in the world (Forbes, Oct 2020) and top patent-holder in the U.S. Want to advance the worlds technology with us?

Job Title: SoC Design Engineer - Design for Test (DFT) Engineer

Req ID: DSA40079

Location: San Jose, CA

OVERVIEW & IMPACT:

As a member of the GNSS ASIC team, the candidate will contribute to the DFT (Design for Test) for low power designs, and to generate/debug DFT patterns in simulation and on ATE.

The candidate should have solid hands-on experience with industry standard DFT techniques such as scan, MBIST and ATE. Job responsibilities include DFT mux insertion, DFT pattern generation, coverage analysis and debug as well as running and debugging gate level simulations. The ideal candidate will have experience in both pre, and post-silicon in the DFT domain.

JOB RESPONSIBILITIES:

As an SoC Design DFT engineer, you will have responsibilities spanning all aspects of DFT:

• Knowledge about industry standards and practices in DFT, ATPG, JTAG, Memory BIST, and trade-offs between test quality and product impact (power, performance, area, schedule)
• Experience in generating and debugging DFT patterns (WGL) in simulation and on ATE
• Experience with running synthesis and developing STA constraints for DFT operation modes
• Experience with Analog DFT and Analog Mixed Signal IP test methods and integration
• Confidence with Verilog, and experience with simulators and waveform debugging tools

QUALIFICATIONS & REQUIRED SKILLS:

The ideal candidate will have 5+ years of DFT experience in low power wireless SoC design with a leading chipset company:

• BS with extensive industry experience or MS is preferred.
• Previous experience in DFT mux, DFT pattern generation.
• Previous experience in analog IP and analog mixed signal IP test.
• Industry exposure to and knowledge of SoC design methodology.
• Also deep knowledge for system design methodologies that contain synthesis, STA, CDC, lint, DFT, EQ, UPF, etc.
• Excellent collaboration skills
• Outstanding written and verbal communication

Additionally, we look for the following universal qualities in all candidates:

• Resourceful Achiever: self-driven and proactive, you apply logic and reason to effectively solve problems and manage risks.
• Avid Learner: you eagerly take on new challenges and seek out opportunities to grow and stretch
• Passionate Owner: you are energized by your work, taking ownership and delivering results without ego
• Committed Collaborator: with a positive attitude and commitment to get to the best result, you welcome ideas from others and drive processes forward in an inclusive manner

EEO Statement

SSI is an Equal Opportunity Employer. It is SSIs policy to comply with all applicable national, state and local laws pertaining to nondiscrimination and equal opportunity, and hiring decisions are made accordingly.